XuanTie C920v2 (Zhihe A210) uarch-tool benchmarks

VLEN: 256

Detect all1s tail/mask policy with simple code snippet:
Tail agnostic policy: undisturbed
Mask agnostic policy: undisturbed
Is vl always set to min(AVL,VLMAX): yes
    Note: spec allows ceil(AVL/2)<=vl<=VLMAX for VLMAX<AVL<2*VLMAX

Measures how LMUL scheduling impacts when results are ready:
A) LMUL=8 v0 overlap with LMUL=1 v0:     216.0812559 cycles/iter
B) LMUL=8 v0 overlap with LMUL=1 v3:     219.5722494 cycles/iter
C) LMUL=8 v0 overlap with LMUL=1 v7:     262.6311197 cycles/iter
D) LMUL=8 v0 overlap with LMUL=1 v8:     198.8904428 cycles/iter
E) LMUL=8 v0 overlap with LMUL=1 v0..v7: 272.9776763 cycles/iter

• The difference between A and C indices that results for the upper part of a vector register group gets completed later than the lower part, even when long dependencies are present.

Measures overhead of reinterpreting a mask as a vector:
A) reinterpret:       15.0160255 cycles/iter
B) don't reinterpret: 10.0081186 cycles/iter

• While A is faster than B, which may indicate that the mask needed to be repacked or a scheduling issue.