RVV benchmark SiFive X280 (Tenstorrent Blackhole)

The Tenstorrent Blackhole is an AI accelerator that among others includes 16 linux capable SiFive X280 cores. The cores runs 1.75 GHz and support the standard V extension with VLEN=512 and DLEN=256.

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Based on this commit.

Thanks to Civil for running the benchmarks.

Benchmarks

• memcpy
• memset
• strlen
• utf8 count
• merge escaped lines
• mandelbrot
• reverse byte order of 32 bit elements
• 4-bit lookup table
• 6-bit lookup table
• histogram
• ascii to utf16 (zero extend 1->2 bytes)
• ascii to utf32 (zero extend 1->4 bytes)
• chacha20
• poly1305
• base64 encode

Performance observations

These are just my first impressions of the core looking at the initial benchmark results.

• the regular vector instructions take 2/4/8/16 cycles for LMUL=1/2/4/8
• The core likes bigger LMUL and vsetvli has basically no overhead (unrolling can still be advantageous, because of the in-order scalar core)
• vl based dispatch, so a LMUL=8 instruction is as fast as a LMUL=1 instruction if vl elements fit into a LMUL=1 register
• 1 cycle per element `vrgather.vv` and `vcompress.vm`, but you can still get decent speed up over scalar loads from memory. (see LUT4 and LUT6)
• Very good fault-only-first load support. Page-size-aware strlen is only about 25% faster than the fault-only-first load version.
• nf=2 segmented load/stores seems very fast. (see utf16)
• nf>2 segmented- and strided load/stores perform decently until a big drop in performance between 8 and 24 KiB of processed data. (see utf32)

Instruction timings

The following are measured cycle averages when unrolling and looping over the given instruction, which should estimate the instruction throughput. The registers involved are randomized to usual values, that is floating point values are real numbers and not NaN/Inf, and instructions like vslide* stay within the vl range. NOTE: The vector arguments couldn't be suitably randomized, I'll have to fix something in the code first.

bench_vaddvx_m1:
m_nop
	li a0, WARMUP
1:
	vadd.vx v8,v16,t0
	vadd.vx v9,v17,t1
	vadd.vx v10,v18,t2
	vadd.vx v11,v19,t3
	vadd.vx v12,v20,t4
	vadd.vx v13,v21,t5
	vadd.vx v14,v22,t6
	vadd.vx v15,v23,t7
	addi a0, a0, -1
	bnez a0, 1b
	li a0, LOOP
	rdcycle a1
1:
.rept UNROLL
	vadd.vx v8,v16,t0
	vadd.vx v9,v17,t1
	vadd.vx v10,v18,t2
	vadd.vx v11,v19,t3
	vadd.vx v12,v20,t4
	vadd.vx v13,v21,t5
	vadd.vx v14,v22,t6
	vadd.vx v15,v23,t7
.endr
	addi a0, a0, -1
	bnez a0, 1b
	fence.i
	rdcycle a0
	sub a0, a0, a1
	ret

bench_vaddvx_m4:
	m_nop
	li a0, WARMUP
1:
	vadd.vx v8,v16,t0
	vadd.vx v12,v20,t4
	vadd.vx v8,v16,t0
	vadd.vx v12,v20,t4
	vadd.vx v8,v16,t0
	vadd.vx v12,v20,t4
	vadd.vx v8,v16,t0
	vadd.vx v12,v20,t4
	addi a0, a0, -1
	bnez a0, 1b
	li a0, LOOP
	rdcycle a1
1:
.rept UNROLL
	vadd.vx v8,v16,t0
	vadd.vx v12,v20,t4
	vadd.vx v8,v16,t0
	vadd.vx v12,v20,t4
	vadd.vx v8,v16,t0
	vadd.vx v12,v20,t4
	vadd.vx v8,v16,t0
	vadd.vx v12,v20,t4
.endr
	addi a0, a0, -1
	bnez a0, 1b
	fence.i
	rdcycle a0
	sub a0, a0, a1
	ret