RVV benchmark Saturn

Saturn is a parameterized open-source RVV 1.0 vector unit integrated into the Chipyard framework. It supports different VLEN and DLEN configurations, as well as "full chaining with zero dead-time". This benchmark was done on the VLEN=256 DLEN=128 configuration connected to a shuttle core, which is a two-issue core based on rocket-chip (GENV256D128ShuttleConfig).
All measurements were done on rtl simulation of the master branch from 2024-08-18.

Additional information:

• "The Saturn Vector Unit: Design of a Fully Compliant Open-Source RISC-V Vector Unit" talk from Jerry Zhao

• Return to parent page

Based on this commit, see wiki page for build instructions.

Benchmarks

• memcpy
• memset
• strlen
• utf8 count
• merge escaped lines
• mandelbrot
• reverse byte order of 32 bit elements
• 4-bit lookup table
• ascii to utf16 (zero extend 1->2 bytes)
• ascii to utf32 (zero extend 1->4 bytes)
• chacha20
• poly1305
• 8x8 transpose SEW=8
• 8x8 transpose SEW=16

Instruction timings

The following are measured cycle averages when unrolling and looping over the given instruction, which should estimate the instruction throughput. The registers involved are randomized to usual values, that is floating point values are real numbers and not NaN/Inf, and instructions like vslide* stay within the vl range Some valid vtype-instruction combinations are missing.

bench_vaddvx_m1:
m_nop
	li a0, WARMUP
1:
	vadd.vx v8,v16,t0
	vadd.vx v9,v17,t1
	vadd.vx v10,v18,t2
	vadd.vx v11,v19,t3
	vadd.vx v12,v20,t4
	vadd.vx v13,v21,t5
	vadd.vx v14,v22,t6
	vadd.vx v15,v23,t7
	addi a0, a0, -1
	bnez a0, 1b
	li a0, LOOP
	rdcycle a1
1:
.rept UNROLL
	vadd.vx v8,v16,t0
	vadd.vx v9,v17,t1
	vadd.vx v10,v18,t2
	vadd.vx v11,v19,t3
	vadd.vx v12,v20,t4
	vadd.vx v13,v21,t5
	vadd.vx v14,v22,t6
	vadd.vx v15,v23,t7
.endr
	addi a0, a0, -1
	bnez a0, 1b
	fence.i
	rdcycle a0
	sub a0, a0, a1
	ret

bench_vaddvx_m4:
	m_nop
	li a0, WARMUP
1:
	vadd.vx v8,v16,t0
	vadd.vx v12,v20,t4
	vadd.vx v8,v16,t0
	vadd.vx v12,v20,t4
	vadd.vx v8,v16,t0
	vadd.vx v12,v20,t4
	vadd.vx v8,v16,t0
	vadd.vx v12,v20,t4
	addi a0, a0, -1
	bnez a0, 1b
	li a0, LOOP
	rdcycle a1
1:
.rept UNROLL
	vadd.vx v8,v16,t0
	vadd.vx v12,v20,t4
	vadd.vx v8,v16,t0
	vadd.vx v12,v20,t4
	vadd.vx v8,v16,t0
	vadd.vx v12,v20,t4
	vadd.vx v8,v16,t0
	vadd.vx v12,v20,t4
.endr
	addi a0, a0, -1
	bnez a0, 1b
	fence.i
	rdcycle a0
	sub a0, a0, a1
	ret

Note: Some results say "time out" because the RTL simulation would've take to long