RVV benchmark MegaBobcat

======BOOM Tile 0 Params======

====Overall Frontend Params====

==L1-ICache==
Fetch bytes   : 16
Block bytes   : 64
Row bytes     : 16
Word bits     : 128
Sets          : 64
Ways          : 8
Refill cycles : 4
RAMs          : (64 x 256) using 2 banks
Dual-banked
I-TLB ways    : 32

==Branch Predictor Memory Sizes==

bank0 tage_l2: 128 x 44 = 704
bank0 tage_l4: 128 x 44 = 704
bank0 tage_l8: 256 x 48 = 1536
bank0 tage_l16: 256 x 48 = 1536
bank0 tage_l32: 128 x 52 = 832
bank0 tage_l64: 128 x 52 = 832
bank0 btb_meta_way0: 128 x 120 = 1920
bank0 btb_data_way0: 128 x 56 = 896
bank0 btb_meta_way1: 128 x 120 = 1920
bank0 btb_data_way1: 128 x 56 = 896
bank0 ebtb: 128 x 40 = 640
bank0 bim: 2048 x 8 = 2048
bank1 tage_l2: 128 x 44 = 704
bank1 tage_l4: 128 x 44 = 704
bank1 tage_l8: 256 x 48 = 1536
bank1 tage_l16: 256 x 48 = 1536
bank1 tage_l32: 128 x 52 = 832
bank1 tage_l64: 128 x 52 = 832
bank1 btb_meta_way0: 128 x 120 = 1920
bank1 btb_data_way0: 128 x 56 = 896
bank1 btb_meta_way1: 128 x 120 = 1920
bank1 btb_data_way1: 128 x 56 = 896
bank1 ebtb: 128 x 40 = 640
bank1 bim: 2048 x 8 = 2048
Total bpd size: 28 KB

====Overall Core Params====

===ExecutionUnits===

==4-wide Machine==
==9 Issue==

==ExeUnit==
 - Mem
==ExeUnit==
 - Mem
==ExeUnit==
 - ALU
 - IFPU
==ExeUnit==
 - ALU
==ExeUnit==
 - ALU
 - Mul
==ExeUnit==
 - ALU
 - Div
==ExeUnit==
 - VecExe

===FP Pipeline===

==Floating Point Regfile==
Num RF Read Ports     : 7
Num RF Write Ports    : 5
RF Cost (R+W)*(R+2W)  : 204
Bypassable Units      : List(false, false, false, false, false)
Num Wakeup Ports      : 5
Num Bypass Ports      : 0

==ROB==
Machine Width      : 4
Rob Entries        : 128
Rob Rows           : 32
Rob Row size       : 5
log2Ceil(coreWidth): 2
FPU FFlag Ports    : 6

===Other Core Params===
Fetch Width           : 8
Decode Width          : 4
Issue Width           : 9
ROB Size              : 128
Issue Window Size     : List(24, 40, 32, 32) (Age-based Priority)
Load/Store Unit Size  : 32/32
Num Int Phys Registers: 128
Num FP  Phys Registers: 128
Max Branch Count      : 20
==Integer Regfile==
Num RF Read Ports     : 14
Num RF Write Ports    : 7
RF Cost (R+W)*(R+2W)  : 588
Bypassable Units      : List(true, true, true, true, true, true, false)

Num Slow Wakeup Ports : 7
Num Fast Wakeup Ports : 4
Num Bypass Ports      : 6

DCache Ways           : 8
DCache Sets           : 64
DCache nMSHRs         : 8
ICache Ways           : 8
ICache Sets           : 64
D-TLB Ways            : 32
I-TLB Ways            : 32
Paddr Bits            : 32
Vaddr Bits            : 39

Using FPU Unit?       : true
Using FDivSqrt?       : true
Using VM?             : true